Domenic Forte

Trusted AI for AMS Design: Causal Insights, Scalable Optimization, and Rapid Failure Diagnostics

University Consulting for Cyber-Informed Engineering

Revisiting the IEEE P1735 Standard for In-house Semiconductor IP Protection

CAMO: Counterfeit Attestation MOdule for Electronics Supply Chain Tracking and Provenance

Causal AI for Interpretable and Robust AMS Topology Synthesis and Optimization

On-Chip Intelligent Sensor Network for Real-Time Anomaly Detection

On-Chip Intelligent Sensor Network for Real-Time Anomaly Detection

Artificially Intelligent SKEPTIC for Context-Aware Decision Validation

Collaborative: SaTC: CORE: Small: ERADICATOR: Techniques for Laser Assisted Side-Channel Attack Monitor & Response

SaTC: TTP: Medium: I-C-U: AI-Enabled Recovery and Assurance of Semiconductor IP from SEM Images

MEST Phase 2

Model Based PCB Attestation

Embry-Riddle - Center for Aerospace Resilience

IP Protection through Secure and Private Function Evaluation - UFL

STAMP: A Holistic Backward/Forward Trust Framework for Protecting Microelectronics Throughout Lifecycle

Hardware Vulnerability Ontology and Database for the Trusted Silicon Stratus

CCRI: ENS: Enhancement of Trust-Hub, a Web-based Portal to support the Cybersecurity Research Community

AutoBoM Phase 2 - Trust and Assurance of Microelectronics (TAME)

STV Phase 3 - Trust and Assurance of Microelectronics (TAME)

Trusted Silicon Stratus (TSS) Vulnerability – Risk Assessment & Mitigation (V-RAM)

ARCHS: Automated Rule Checking for Hardware Security

Protection for Critical Technology: Pre-Silicon Security Verification and Backside Protection Schemes for Microelectronic Devices

NSF Student Travel Grant for 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST): San Jose, CA - May 2020

Security-Aware FSM Design Flow for Identifying and Mitigating Fault Attacks

2D/3D Data Collection of PCB Surface Mount Components for Automated Bill of Material Generation